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[ak4372] ms0684-e-02 2008/12 - 1 - general description the ak4372 is a 24-bit dac with an integrated p ll and headphone amplifier. the pll input frequency is synchronized to typical mobile phone clock frequenc ies. the ak4372 features an analog mixing circuit that allows easy interfacing in mobile phone and portable communi cation designs. the integrated headphone amplifier features ?pop-noise free? power-on/ off, a mute control, and it delivers 40mw of power into 16 . the ak4372 is packaged in a 24-pin csp (2 .5mm2.5mm) package, ideal for portable applications. feature ? multi-bit ? dac ? sampling rate - 8khz ~ 48khz ? on chip perfect filtering 8 times fir interpolator - passband: 20khz - passband ripple: 0.02db - stopband attenuation: 54db ? digital de-emphasis filter: 32khz, 44.1khz and 48khz ? system clock - pll mode (mcki): 27mhz, 26mhz, 19. 8mhz, 19.68mhz, 19. 2mhz, 15.36mhz, 14.4mhz, 13mhz, 12m hz and 11.2896mhz - pll mode (bick or lrck): 64fs, 32fs or fs - ext mode: 256fs/384fs/512fs/768fs/1024fs - input level: ac couple input available ? audio i/f format: msb first, 2?s complement - i 2 s, 24bit msb justified, 24bit/20bit/16bit lsb justified - master/slave mode ? digital mixing: lr, ll, rr, (l+r)/2 ? bass boost function ? digital att ? analog mixing circuit: 3 inputs (si ngle-ended or full-differential) ? stereo lineout - s/n: 90db@3.3v - output volume: +6 to ?24db (or 0 to ?30db), 2db step ? headphone amplifier - output power: 40mw x 2ch @16 , 3.3v - s/n: 92db@3.3v - pop noise free at power-on/off and mute - output volume: 0 ~ ?63db & +12/+6/0 db gain 1.5db step (0 ~ ?30db), 3db step (?30 ~ ?63db) ? p interface: 3-wire/i 2 c ? power supply: 1.6v 3.6v ? power supply current: 3.8ma @1.8v (6.8mw, dac+hp, no output) ? ak4372ecb: ta= ? 30 85 c ak4372vcb: ta= ? 40 85 c ? small package: 24pin csp (2.5mm x 2.5mm, 0.4mm pitch) ? register compatible with ak4368 dac with built-in pll & hp-amp ak4372
[ak4372] ms0684-e-02 2008/12 - 2 - block diagram audio interface hdp amp serial i/f hpl hpr lout rin/in+ sdata lrck cad0/csn bick scl/cclk sda/cdti mutet vcom dac dac lin / in ? (lch) (rch) vcom pll mcki digital volume bass boost de- emphasis digital filter mute pdn mcko vcoc rout dvdd avdd vss1 vss2 hdp amp mute i2c min figure 1. block diagram
[ak4372] ms0684-e-02 2008/12 - 3 - ordering guide ak4372ecb ? 30 +85 c 24pin csp (0.4mm pitch) black type ak4372vcb ? 40 +85 c 24pin csp (0.4mm pitch) black type AKD4372 evaluation board for ak4372 pin layout a bc e d 5 3 4 1 2 top view 5 vss2 cclk csn pdn mutet 4 vcoc mcko cdti lout rout 3 mcki lrck dvdd i2c vcom 2 bick lin hpr avdd 1 sdata rin min hpl vss1 a b c d e top view
[ak4372] ms0684-e-02 2008/12 - 4 - comparison with ak4370/71 1 function function ak4370 ak4371 ak4372 analog mixing 2-stereo single-ended input or full-differential input 3-stereo single-ended input or full-differential input 1-stereo + 1-mono single-ended input or full-differential input pll no yes yes internal vref no yes no hands-free amp no yes no ta ? 30 +85 c ? 30 +85 c ak4372ecb: ? 30 +85 c ak4372vcb: ? 40 +85 c package 24 pin qfn (4mm x 4mm, 0.5mm pitch) 32 pin qfn (4mm x 4mm, 0.4mm pitch) 24 pin csp (2.5mm x 2.5mm, 0.4mm pitch) 2 register (difference from ak4370/71) addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 0 pmvref pmpll pmlo muten pmhpr pmhpl pmdac pmvcm 01h pll control fs3 fs2 fs1 fs0 pll3 pll2 pll1 pll0 02h clock control pll4 0 m/s mckac bf ps0 ps1 mcko 03h mode control 0 0 mono1 mono0 bckp lrp dif2 dif1 dif0 04h mode control 1 ats dattc lmute smute bst1 bst0 dem1 dem0 05h dac lch att attl7 attl6 attl5 attl4 a ttl3 attl2 attl1 attl0 06h dac rch att attr7 attr6 attr5 attr4 a ttr3 attr2 attr1 attr0 07h headphone out select 0 hpg1 hpg0 minhr minhl rinhr linhl darhr dalhl 08h lineout select 0 0 log minr minl rinr linl darr dall 09h lineout att 0 0 0 0 atts3 atts2 atts1 atts0 0ah reserved 0 0 0 0 0 0 0 0 0bh reserved 0 0 0 0 0 0 0 0 0ch reserved 0 0 0 0 0 0 0 0 0dh headphone out select 1 rin3 h r rin3 h l lin3 h r lin3 h l rin2 h r rin2 h l linhr rinhl 0eh headphone att 0 hpz hmute atth4 atth3 atth2 atth1 atth0 0fh lineout select 1 rin3r rin3l lin3r lin3l rin2r rin2l linr rinl 10h mono mixing 0 0 l3m l3hm l2m l2 hm lm lhm 11h differential select 0 0 0 0 0 ldifm ldifh ldif 12h reserved rin3m lin3m rin2m lin2m rin1m lin1m darm dalm 13h reserved 0 pmmo mog mmute attm3 attm2 attm1 attm0 these bits are changed from the ak4370/71. these bits are deleted in the ak4372. these bits are deleted in the ak4370.
[ak4372] ms0684-e-02 2008/12 - 5 - pin/function no. pin name i/o function a1 sdata i audio serial data input pin b2 bick i/o audio serial data clock pin b3 lrck i/o input / output channel clock pin a3 mcki i external master clock input pin c3 dvdd - digital power supply pin, 1.6 3.6v a4 vcoc o output for loop filter of pll circuit this pin must be connected to vss2 with one resistor and one capacitor in series. a5 vss2 - ground 2 pin. connected to vss1. b4 mcko o master clock output pin sda i/o control data input/output pin (i2c mode : i2c pin = ?h?) c4 cdti i control data input pin (3-wire serial mode : i2c pin = ?l?) scl i control data clock pin (i2c mode : i2c pin = ?h?) b5 cclk i control data clock pin (3-wire serial mode : i2c pin = ?l?) cad0 i chip address 0 select pin (i2c mode : i2c pin = ?h?) c5 csn i chip select pin (3-wire serial mode : i2c pin = ?l?) d5 pdn i power-down & reset when ?l?, the ak4372 is in power-down mode and is held in reset. the ak4372 must be reset once upon power-up. d3 i2c i control mode select pin ?h?: i 2 c bus, ?l?: 3-wire serial e5 mutet o mute time constant control pin connected to the vss1 pin with a capacitor for mute time constant. d4 lout o lch stereo line output pin e4 rout o rch stereo line output pin e3 vcom o common voltage output pin normally connected to th e vss1 pin with a 2.2 f electrolytic capacitor. e2 avdd - analog & pll power supply pin, 1.6 3.6v e1 vss1 - ground 1 pin d2 hpr o rch headphone amp output d1 hpl o lch headphone amp output c1 min i mono analog input pin rin i rch analog input pin (ldif bit =?0? : single-ended input) b1 in+ i positive line input pin (ldif bit =?1? : full-differential input) lin i rch analog input pin (ldif bit =?0? : single-ended input) c2 in ? i negative line input pin (ldif bit =?1? : full-differential input ) note 1. all digital input pins (i2c, sda/cdti, scl/cclk, cad0/csn, sdata, lrck, bick, mcki, pdn) must not be left floating. the mcki pin can be left floating only when the pdn pin = ?l?.
[ak4372] ms0684-e-02 2008/12 - 6 - handling of unused pin the unused i/o pins must be processed appropriately as below. classification pin name setting analog lout, rout, mutet, hpr, hpl, min, rin/in+, lin/in ? these pins must be open. mcki this pin must be connected to vss2. digital mcko this pin must be open. absolute maximum rating (vss1 = vss2 =0v; note 2 , note 3 ) parameter symbol min max units power supplies analog avdd ? 0.3 4.6 v digital dvdd ? 0.3 4.6 v input current (any pins except for supplies) iin - 10 ma analog input voltage ( note 4 ) vina ? 0.3 (avdd+0.3) or 4.6 v digital input voltage ( note 5 ) vind ? 0.3 (dvdd+0.3) or 4.6 v ak4372ecb ta ? 30 85 c ambient temperature ak4372vcb ta ? 40 85 c storage temperature tstg ? 65 150 c note 2. all voltages with respect to ground. note 3. vss1 and vss2 must be connected to the same analog ground plane. note 4. lin/in , rin/in+ and min pins. max is smalle r value between (avdd+0.3)v and 4.6v. note 5. sda/cdti, scl/cclk, cad0/csn, sdata, lrck, bick, mcki, pdn and i2c pins. max is smaller value between (dvdd+0.3)v and 4.6v. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommend operating conditions (vss1 = vss2 =0v; note 2 ) parameter symbol min typ max units power supplies analog avdd 1.6 2.4 3.6 v ( note 6 ) digital ( note 7 ) dvdd 1.6 2.4 (avdd+0.2) or 3.6 v note 1. all voltages with respect to ground. note 6. when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. when the ak4372 is powered-down, dvdd should be powered-down at the same time or later than avdd. note 7. max is smaller value between (avdd+0.2)v and 3.6v. * akemd assumes no responsibility for usage beyond the conditions in this datasheet.
[ak4372] ms0684-e-02 2008/12 - 7 - analog characteristics (ta=25 c; avdd=dvdd=2.4v, vss1=vss2=0v; fs=44.1khz; ext mode; boost off; slave mode; signal frequency =1khz; measurement band width=20hz 20khz; headphone-amp: load impedance is a serial connection with r l =16 and c l =220 f. (refer to figure 50 ; unless otherwise specified) parameter min typ max units dac resolution - - 24 bit headphone-amp: (hpl/hpr pins) ( note 8 ) analog output characteristics thd+n ? 3dbfs output, 2.4v, po=10mw@16 - ? 50 ? 40 db 0dbfs output, 3.3v, po=40mw@16 - ? 20 - db ? 60dbfs output, a-weighted, 2.4v 82 90 - db d-range ? 60dbfs output, a-weighted, 3.3v - 92 - db a-weighted, 2.4v 82 90 - db s/n a-weighted, 3.3v - 92 - db interchannel isolation 60 80 - db dc accuracy interchannel gain mismatch - 0.3 0.8 db gain drift - 200 - ppm/ c load resistance ( note 9 ) 16 - - load capacitance - - 300 pf ? 3dbfs output ( note 10 ) 1.04 1.16 1.28 vpp output voltage 0dbfs output, 3.3v, po=40mw@16 - 0.8 - vrms output volume: (hpl/hpr pins) step size 0 ?30db 0.1 1.5 2.9 db (hpg1-0 bits = ?00?) ?30 ?63db 0.1 3 5.9 db gain control range max (att4-0 bits = 00h) - 0 - db (hpg1-0 bits = ?00?) min (att4-0 bits = 1fh) - ? 63 - db stereo line output: (lout/rout pins, r l =10k ) ( note 11 ) analog output characteristics: thd+n (0dbfs output) - ? 60 ? 50 db s/n a-weighted, 2.4v 80 87 - db a-weighted, 3.3v - 90 - db dc accuracy gain drift - 200 - ppm/ c load resistance ( note 9 ) 10 - - k load capacitance - - 25 pf output voltage (0dbfs output) ( note 12 ) 1.32 1.47 1.61 vpp output volume: (lout/rout pins) step size 1 2 3 db gain control range max (atts3-0 bits = fh) - 0 - db (log1-0 bit = ?0?) min (atts3-0 bits = 0h) - ? 30 - db note 8. dalhl=darhr bits = ?1?, linhl=ri nhl=minhl=linhr=rinhr=minhr bits = ?0?. note 9. ac load. note 10. output voltage is proportional to avdd voltage. vout = 0.48 x avdd(typ)@ ? 3dbfs. note 11. dall=darr bits = ?1?, linl=r inl=minl=linr=rinr=minr bits = ?0? note 12. output voltage is proportional to avdd voltage. vout = 0.61 x avdd(typ)@0dbfs.
[ak4372] ms0684-e-02 2008/12 - 8 - parameter min typ max units linein: (lin/rin/min pins) analog input characteristics input resistance (see figure 25 , figure 26 , figure 27 ) lin pin linhl=linhr=linl=linr= bits = ?1? 14 25 - k linhl bit = ?1?, linhr=linl=linr bits = ?0? - 100 - k linhr bit = ?1?, linhl=linl=linr bits = ?0? - 100 - k linl bit = ?1?, linhl=linhr=linr bits = ?0? - 100 - k linr bit = ?1?, linhl=linhr=linl bits = ?0? - 100 - k rin pin rinhl=rinhr=rinl=rinr bits = ?1? 14 25 - k rinhl bit = ?1?, rinhr=rinl=rinr bits = ?0? - 100 - k rinhr bit = ?1?, rinhl=rinl=rinr bits = ?0? - 100 - k rinl bit = ?1?, rinhl=rinhr=rinr bits = ?0? - 100 - k rinr bit = ?1?, rinhl=rinhr=rinl bits = ?0? - 100 - k min pin minhl=minhr=minl=minr bits = ?1? 14 25 - k minhl bit = ?1?, minhr=minl=minr bits = ?0? - 100 - k minhr bit = ?1?, minhl=minl=minr bits = ?0? - 100 - k minl bit = ?1?, minhl=minhr=minr bits = ?0? - 100 - k minr bit = ?1?, minhl=minhr=minl bits = ?0? - 100 - k gain lin/rin/min ? lout/rout ? 1 0 +1 db lin/rin/min ? hpl/hpr ? 0.05 +0.95 +1.95 db power supplies power supply current normal operation (pdn pin = ?h?) ( note 13 ) avdd+dvdd - 5.0 8.0 ma power-down mode (pdn pin = ?l?) ( note 14 ) - 1 100 a note 13. pmdac=pmhpl=pmhpr=pmlo bits = ?1?, muten bit = ?1?, mcko bit = ?0?, hp-amp no output. pmdac=pmhpl=pmhpr= ?1?, pmlo bit= ?0?, avdd+ dvdd=4.0ma (typ) @2.4v, 3.8ma (typ) @1.8v. note 14. all digital input pins are fixed to vss2.
[ak4372] ms0684-e-02 2008/12 - 9 - filter characteristics (ta=25 c; avdd = dvdd=1.6 3.6v; fs=44.1khz; de-emphasis = off) parameter symbol min typ max units dac digital filter: ( note 15 ) passband ( note 16 ) ? 0.05db pb 0 - 20.0 khz ? 6.0db - 22.05 - khz stopband ( note 16 ) sb 24.1 - - khz passband ripple pr - - 0.02 db stopband attenuation sa 54 - - db group delay ( note 17 ) gd - 22 - 1/fs group delay distortion gd - 0 - s dac digital filter + analog filter: ( note 15 , note 18 ) frequency response 0 20.0khz fr - 0.5 - db analog filter: ( note 19 ) frequency response 0 20.0khz fr - 1.0 - db boost filter: ( note 18 , note 20 ) 20hz fr - 5.76 - db 100hz - 2.92 - db min 1khz - 0.02 - db 20hz fr - 10.80 - db 100hz - 6.84 - db mid 1khz - 0.13 - db 20hz fr - 16.06 - db 100hz - 10.54 - db frequency response max 1khz - 0.37 - db note 15. boost off (bst1-0 bit = ?00?) note 16. the passband and stopband frequencies scale with fs (system sampling rate). for example, pb=0.4535fs(@ ? 0.05db). sb=0.546fs(@ ? 54db). note 17. this time is from setting the 24-bit data of both channels from the input register to the output of analog signal. note 18. dac ? hpl, hpr, lout, rout note 19. lin/min ? hpl/lout, rin/min ? hpr/rout note 20. these frequency responses scale with fs. if high- level signal is input, the output clips at low frequency. boost filter (fs=44.1khz) -5 0 5 10 15 20 10 100 1000 10000 frequency [hz] gain [db] max mid min figure 2. boost frequency (fs=44.1khz)
[ak4372] ms0684-e-02 2008/12 - 10 - dc characteristics (ta=25 c; avdd = dvdd=1.6 3.6v) parameter symbol min typ max units high-level input voltage 2.2v dvdd 3.6v vih 70 % dvdd - - v 1.6v dvdd<2.2v vih 80 % dvdd - - v low-level input voltage 2.2v dvdd 3.6v vil - - 30 % dvdd v 1.6v dvdd<2.2v vil - - 20 % dvdd v input voltage at ac coupling ( note 21 ) vac 0.4 - - vpp high-level output voltage (iout= ? 200 a) voh dvdd ? 0.2 - - v low-level output voltage (except sda pin: iout=200 a) vol - - 0.2 v (sda pin, 2.0v dvdd 3.6v: iout=3ma) vol - - 0.4 v (sda pin, 1.6v dvdd<2.0v: iout=3ma) vol - - 20%dvdd v input leakage current iin - - 10 a note 21. the mcki pin is connected to a capacitor. ( figure 50 )
[ak4372] ms0684-e-02 2008/12 - 11 - switching characteristics (ta=25 c; avdd = dvdd=1.6 3.6v; c l = 20pf; unless otherwise specified) parameter symbol min typ max units master clock input timing frequency (pll mode) fclk 11.2896 - 27 mhz (ext mode) fclk 2.048 - 24.576 mhz pulse width low ( note 22 ) tclkl 0.4/fclk - - ns pulse width high ( note 22 ) tclkh 0.4/fclk - - ns ac pulse width ( note 23 ) tacw 18.5 - - ns lrck timing frequency fs 8 44.1 48 khz duty cycle: slave mode duty 45 - 55 % master mode duty - 50 - % mcko output timing (pll mode) frequency fclko 0.256 - 12.288 mhz duty cycle (except fs=32khz, ps1-0= ?00?) dmck 40 - 60 % (fs=32khz, ps1-0= ?00?) dmck - 33 - % serial interface timing ( note 24 ) slave mode (m/s bit = ?0?): bick period ( note 25 ) (except pll mode, pll4-0 bit = ?01110?, ?01111?) tbck 312.5 or 1/(64fs) - 1/(32fs) ns (pll mode, pll4-0 bits = ?01110?) tbck - 1/(32fs) - ns (pll mode, pll4-0 bits = ?01111?) tbck - 1/(64fs) - ns bick pulse width low (except pll mode, pll4-0 bit = ?01110?, ?01111?) tbckl 100 - - ns (pll mode, pll4-0 bit = ?01110?, ?01111?) tbckl 0.4 x tbck - - ns bick pulse width high (except pll mode, pll4-0 bit = ?01110?, ?01111?) tbckh 100 - - ns (pll mode, pll4-0 bit = ?01110?, ?01111?) tbckh 0.4 x tbck - - ns lrck edge to bick ? ? ( note 26 ) tlrb 50 - - ns bick ? ? to lrck edge ( note 26 ) tblr 50 - - ns sdata hold time tsdh 50 - - ns sdata setup time tsds 50 - - ns master mode (m/s bit = ?1?): bick frequency (bf bit = ?1?) fbck - 64fs - hz (bf bit = ?0?) fbck - 32fs - hz bick duty dbck - 50 - % bick ? ? to lrck tmblr ? 50 - 50 ns sdata hold time tsdh 50 - - ns sdata setup time tsds 50 - - ns control interface timing (3-wire serial mode) cclk period tcck 200 - - ns cclk pulse width low tcckl 80 - - ns pulse width high tcckh 80 - - ns cdti setup time tcds 40 - - ns cdti hold time tcdh 40 - - ns csn ?h? time tcsw 150 - - ns csn edge to cclk ? ? ( note 27 ) tcss 50 - - ns cclk ? ? to csn edge ( note 27 ) tcsh 50 - - ns
[ak4372] ms0684-e-02 2008/12 - 12 - parameter symbol min typ max units control interface timing (i 2 c bus mode): ( note 28 ) scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 29 ) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s capacitive load on bus cb - - 400 pf pulse width of spike noise suppressed by input filter tsp 0 - 50 ns power-down & reset timing pdn pulse width ( note 30 ) tpd 150 - - ns note 22. except ac coupling. note 23. pulse width to ground level when the mcki pin is connected to a capacitor in series and a resistor is connected to ground. (refer to figure 3 .) note 24. refer to ?serial data interface?. note 25. min is longer value between 312.5ns or 1/(64f s) except for pll mode, pll4-0 bits = ?01110?, ?01111?. note 26. bick rising edge must not occur at the same time as lrck edge. note 27. cclk rising edge must not occur at the same time as csn edge. note 28. i 2 c is a registered trademark of philips semiconductors. note 29. data must be held long enough to bridge the 300ns-transition time of scl. note 30. when power-up, the ak4372 can be reset by bringing pdn pin = ?h? from ?l?.
[ak4372] ms0684-e-02 2008/12 - 13 - timing diagram mcki input measurement point vss2 tacw t acw vss2 1/fclk 1000pf 100k vac figure 3. mcki ac coupling timing 1/fclk tclkl vih tclkh mcki vil 1/fs vih lrck vil tbck tbckl vih tbckh bick vil tl 50% dvdd th mcko dmck=th/(th+tl) or tl/(th+tl) figure 4. clock timing
[ak4372] ms0684-e-02 2008/12 - 14 - tlrb lrck vih bick vil tsds vih sdata vil tsdh vih vil tblr figure 5. serial interf ace timing (slave mode) lrck 50%dvdd bick tsds vih sdata vil tsdh 50%dvdd tmblr figure 6. serial interf ace timing (master mode)
[ak4372] ms0684-e-02 2008/12 - 15 - csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck tcsh figure 7. write command input timing csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 tcss figure 8. write data input timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 9. i 2 c bus mode timing tpd vil pdn figure 10. power-down & reset timing
[ak4372] ms0684-e-02 2008/12 - 16 - operation overview system clock there are the following six clock modes to interface with external devices ( table 1 and table 2 ). mode pmpll bit m/s bit pll3-0 bits figure pll master mode 1 1 see table 4 figure 11 pll slave mode 1 (pll reference clock: mcki pin) 1 0 see table 4 figure 12 pll slave mode 2 (pll reference clock: bick pin) 1 0 see table 4 figure 13 pll slave mode 3 (pll reference clock: lrck pin) 1 0 see table 4 figure 14 ext master mode 0 1 x figure 15 ext slave mode 0 0 x figure 16 table 1. clock mode setting (x: don?t care) mode mcko bit mcko pin mcki pin bick pin lrck pin 0 l pll master mode 1 selected by ps1-0 bits selected by pll4-0 bits output (selected by bf bit) output (1fs) 0 l pll slave mode 1 (pll reference clock: mcki pin) 1 selected by ps1-0 bits selected by pll4-0 bits input (32fs 64fs) input (1fs) pll slave mode 2 (pll reference clock: bick pin) 0 l gnd input (selected by pll4-0 bits) input (1fs) pll slave mode 3 (pll reference clock: lrck pin) 0 l gnd input (32fs 64fs) input (1fs) ext master mode 0 l selected by fs3-0 bits output (selected by bf bit) output (1fs) ext slave mode 0 l selected by fs3-0 bits input (32fs 64fs) input (1fs) table 2. clock pins state in clock mode master mode/slave mode the m/s bit selects either master or sl ave mode. m/s bit = ?1? selects master m ode and ?0? selects slave mode. when the ak4372 is power-down mode (pdn pin = ?l?) and exits reset st ate, the ak4372 is slave mode. after exiting reset state, the ak4372 changes to master mode by setting m/s bit = ?1?. when the ak4372 is in master mode, the lrck and bick pins are a floating state until m/s bit becomes ?1?. the lrck and bick pins of the ak4372 should be pulled-down or pulled-up by a resistor (about 100k ) externally to avoid the floating state. m/s bit mode 0 slave mode (default) 1 master mode table 3. select master/slave mode
[ak4372] ms0684-e-02 2008/12 - 17 - pll mode (pmpll bit = ?1?) when pmpll bit is ?1?, a fully integrated analog phase lock ed loop (pll) generates a clock that is selected by the pll4-0 and fs3-0 bits ( table 4 , table 5 , table 6 ). the pll lock time is shown in table 4 , whenever the ak4372 is supplied to a stable clocks after pll is powered-up (pmpll bit = ?0? ?1?) or sampling frequency changes. 1) setting of pll mode mode r,c at vcoc pll4 pll3 pll2 pll1 pll0 reference clock fs ( note 31 ) r[ ] c[f] pll lock time (typ) 0 0 0 0 0 0 mcki 11.2896mhz type 1 10k 22n 20ms (default) 1 0 0 0 0 1 mcki 14.4mhz type 1 10k 22n 20ms 2 0 0 0 1 0 mcki 12mhz type 1 10k 47n 20ms 3 0 0 0 1 1 mcki 19.2mhz type 1 10k 22n 20ms 4 0 0 1 0 0 mcki 15.36mhz type 1 10k 22n 20ms 5 0 0 1 0 1 mcki 13mhz type 1 15k 330n 100ms 6 0 0 1 1 0 mcki 19.68mhz type 1 10k 47n 20ms 7 0 0 1 1 1 mcki 19.8mhz type 1 10k 47n 20ms 8 0 1 0 0 0 mcki 26mhz type 1 15k 330n 100ms 9 0 1 0 0 1 mcki 27mhz type 1 10k 47n 20ms 10 0 1 0 1 0 mcki 13mhz type 2 10k 22n 20ms 11 0 1 0 1 1 mcki 26mhz type 2 10k 22n 20ms 12 0 1 1 0 0 mcki 19.8mhz type 3 10k 22n 20ms 13 0 1 1 0 1 mcki 27mhz type 4 10k 22n 20ms 14 0 1 1 1 0 bick 32fs table 6 6.8k 47n 20ms 15 0 1 1 1 1 bick 64fs table 6 6.8k 47n 20ms 16 1 0 0 0 0 lrck fs table 6 6.8k 330n 80ms others others n/a note 31. refer to table5 about type1-4 note 32 : clock jitter is lower in mode10-13 than mode5/ 7/ 8/ 9 respectively note 33. modes 14~16 are available at slave mode only. table 4. setting of pll mode (*fs: sampling frequency, n/a: not available) 2) setting of sampling frequency in pll mode when pll reference clock input is mcki pin, the sampli ng frequency is selected by fs3-0 bits as defined in table 5 . fs mode fs3 fs2 fs1 fs0 type 1 type 2 type 3 type 4 0 0 0 0 0 48khz 48.0007khz 47.9992khz 47.9997khz 1 0 0 0 1 24khz 24.0004khz 23.9996khz 23.9999khz 2 0 0 1 0 12khz 12.0002khz 11.9998khz 11.9999khz 4 0 1 0 0 32khz 32.0005khz 31.9994khz 31.9998khz 5 0 1 0 1 16khz 16.0002khz 15.9997khz 15.9999khz 6 0 1 1 0 8khz 8.0001khz 7.9999khz 7.9999khz 8 1 0 0 0 44.1khz 44.0995khz 44.0995khz 44.0995khz (default) 9 1 0 0 1 22.05khz 22.0498khz 22.0498khz 22.0498khz 10 1 0 1 0 11.025khz 11.0249khz 11.0249khz 11.0249khz 3, 7, 11-15 others n/a n/a n/a n/a table 5. setting of sampling frequency (pll reference cl ock input is the mcki pin) (n/a: not available)
[ak4372] ms0684-e-02 2008/12 - 18 - when pll reference clock input is the lrck or bick pin, the sampling frequency is selected by fs3-0 bits. ( table 6 ) mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 1 0 0 0 32khz < fs 48khz (default) 1 1 0 0 1 24khz < fs 32khz 2 1 0 1 0 16khz < fs 24khz 3 1 0 1 1 12khz < fs 16khz 4 1 1 0 0 8khz fs 12khz others others n/a table 6. setting of sampling frequency (pll reference cloc k input is lrck or bick pin) (n/a: not available) pll unlock state 1) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in master mode (m/s bits = ?1?), the lrck and bick pins output ?l? before the pll is locked by setting pmpll = pmdac bits = ?0? ? ?1?. at that time, the mcko pin outputs an i rregular frequency clock at mcko bit = ?1?. when mcko bit = ?0?, the mcko pin outputs ?l?. after the pll is locked, the lrck and bick start outputting the clocks ( table 7 ). master mode (m/s bit = ?1?) power up (pmdac bit= pmpll bit= ?1?) power down (pmdac bit= pmpll bit= ?0?) pll unlock mcki pin refer to table 4 . input or fixed to ?l? or ?h? externally refer to table 4 . mcko pin mcko bit = ?0?: ?l? mcko bit = ?1?: output l mcko bit = ?0?: l mcko bit = ?1?: unsettling bick pin bf bit = ?1?: 64fs output bf bit = ?0?: 32fs output l l lrck pin output l l table 7. clock operation in master mode (pll mode) 2) pll slave mode (pmpll b it = ?1?, m/s bit = ?0?) in slave mode (m/s bits = ?0?), an invalid clock is output from the mcko pin when mcko bit = ?1?, before the pll is locked by setting pmpll = pmdac bits = ?0? ? ?1?. when mcko bit = ?0?, the mcko pin outputs ?l?. after the pll is locked, the mcko pin starts outputting the clocks ( table 9 ). slave mode (m/s bit = ?0?) power up (pmdac bit= pmpll bit= ?1?) power down (pmdac bit= pmpll bit= ?0?) pll unlock mcki pin refer to table 4 . input or fixed to ?l? or ?h? externally refer to table 4 . mcko pin mcko bit = ?0?: ?l? mcko bit = ?1?: output l mcko bit = ?0?: l mcko bit = ?1?: unsettling bick pin input fixed to ?l? or ?h? externally input or fixed to ?l? or ?h? externally lrck pin input fixed to ?l? or ?h? externally input or fixed to ?l? or ?h? externally table 8. clock operation in slave mode (pll mode)
[ak4372] ms0684-e-02 2008/12 - 19 - pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (11.2896mhz, 12mhz, 13mhz, 14.4mhz, 15.36mhz, 19.2mhz, 19.68mhz,19.8mhz, 26mhz or 27mhz) is input to the mcki pin, the mcko, bick and lrck clocks are generated by an internal pll circuit. the mcko output frequency is selected by ps1-0 bits ( table 9 ) and the output is enabled by mcko bit. the bick output frequency is selected between 32fs or 64fs, by bf bit ( table 10 ). ak4372 dsp or p mcko bick lrck sdata bclk lrck sdto mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 27mhz,26mhz,19.8mhz,19.68mhz, 19.2mhz,15.36mhz,14.4mhz,13mhz, 12mhz,11.2896mhz mclk figure 11. pll master mode ps1 ps0 mcko 0 0 256fs (default) 0 1 128fs 1 0 64fs 1 1 32fs table 9. mcko frequency (pll mode, mcko bit = ?1?) bf bit bick frequency 0 32fs (default) 1 64fs table 10. bick output frequency at master mode
[ak4372] ms0684-e-02 2008/12 - 20 - pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to the mcki, bick or lrck pin. the required clock to the ak4372 is generated by an internal pll circuit. input frequency is selected by pll4-0 bits ( table 4 ). a) pll reference clock: mcki pin bick and lrck inputs should be synchronized with mcko output. the phase between mcko and lrck dose not matter. the mcko pin outputs the frequency selected by ps1-0 bits ( table 9 ) and the output is enabled by mcko bit. sampling frequency can be selected by fs3-0 bits ( table 5 ). the external clocks (mcki, bick and lrck) should always be present whenever the dac is in operation (pmdac bit = ?1?). if these clocks are not provided, the ak4372 may draw excess current and will not possible to operate properly because it utilizes dynamic refreshed logic internally. if the external clocks are not present, the dac should be in the power-down mode (pmdac bits = ?0?). ak4372 dsp or p mcko bick lrck sdata bclk lrck sdto mcki 1fs 32fs ~ 64fs 256fs/128fs/64fs/32fs 27mhz,26mhz,19.8mhz,19.68mhz, 19.2mhz,15.36mhz,14.4mhz,13mhz, 12mhz,11.2896mhz mclk figure 12. pll slave mode (pll reference clock: mcki pin) b) pll reference clock: bick pin sampling frequency corresponds to 8khz to 48khz by changing fs3-0 bits ( table 6 ). ak4372 dsp or p mcko bick lrck sdata bclk lrck sdto mcki 1fs 32fs or 64fs figure 13. pll slave mode (pll reference clock: bick pin)
[ak4372] ms0684-e-02 2008/12 - 21 - c) pll reference clock: lrck pin sampling frequency corresponds to 8khz to 48khz by changing fs3-0 bits ( table 6 ). ak4372 dsp or p mcko bick lrck sdata bclk lrck sdto mcki 1fs 32fs 64fs figure 14. pll slave mode (pll reference clock: lrck pin)
[ak4372] ms0684-e-02 2008/12 - 22 - ext mode (pmpll bit = ?0?: default) the ak4372 can be placed in external clock mode (ext m ode) by setting the pmpll bit to ?0?. in ext mode, the master clock can directly input to the dac via the mcki pin without going through the pll. in this case, the sampling frequency and mcki frequency can be selected by fs3-0 bits ( table 11 ). in ext mode, pll4-0 bits are ignored. mcko output is enabled by mcko bit. the mcko output frequency can be controlled by ps1-0 bits. if the sampling frequency is changed during normal operation of the dac (pmdac bit = ?1?), the input must be muted by smute bit = ?1?, or set to ?0? data. lrck and bick are output from the ak4372 in master mode( figure 15 ). the clock input to the mcki pin should always be present whenever the dac is in normal operation (pmdac bit = ?1?). if these clocks are not provided, the ak4372 may draw excessive current and w ill not operate properly because it utilizes these clocks for internal dynamic refresh of registers. if the external cl ocks are not present, the dac should be placed in power-down mode (pmdac bit = ?0?). ak4372 dsp or p mcki bick lrck sdata bclk lrck sdto mcko 1fs 32fs, 64fs mclk 256fs, 384fs, 512fs, 768fs or 1024fs figure 15. ext master mode the external clocks required to operate the ak4372 in slave mode are mcki, lrck and bick( figure 16 ). the master clock (mcki) should be synchronized with the sampling clock (lrck). the phase between these clocks does not matter. all external clocks (mcki, bick and lrck) should always be present whenever the dac is in normal operation mode (pmdac bit = ?1?). if these clocks are not provided, th e ak4372 may draw excessive cu rrent and will not operate properly, because it utilizes these clocks fo r internal dynamic refresh of registers. if the external clocks are not present, t he dac should be placed in power- down mode (pmdac bit = ?0?). ak4372 dsp or p mcki bick lrck sdata bclk lrck sdto mcko 1fs 32fs, 64fs mclk 256fs, 384fs, 512fs, 768fs or 1024fs figure 16. ext slave mode
[ak4372] ms0684-e-02 2008/12 - 23 - mode fs3 fs2 fs1 fs0 fs mcki 0 0 0 0 0 8khz 48khz 256fs 1 0 0 0 1 8khz 48khz 512fs 2 0 0 1 0 8khz 24khz 1024fs 4 0 1 0 0 8khz 48khz 256fs 5 0 1 0 1 8khz 48khz 512fs 6 0 1 1 0 8khz 24khz 1024fs 8 1 0 0 0 8khz 48khz 256fs (default) 9 1 0 0 1 8khz 48khz 512fs 10 1 0 1 0 8khz 24khz 1024fs 12 1 1 0 0 8khz 48khz 384fs 13 1 1 0 1 8khz 24khz 768fs others others n/a n/a table 11. relationship between sampling frequency and mcki frequency (ext mode) (n/a: not available) ps1 ps0 mcko 0 0 256fs (default) 0 1 128fs 1 0 64fs 1 1 32fs table 12. mcko frequency (ext mode, mcko bit = ?1?) master mode (m/s bit = ?1?) power up (pmdac bit = ?1?) po wer down (pmdac bit = ?0?) mcki pin refer to table 11 input or fixed to ?l? or ?h? externally mcko pin mcko bit = ?0?: l mcko bit = ?1?: output l bick pin bf bit = ?1?: 64fs output bf bit = ?0?: 32fs output l lrck pin output l table 13. clock operation in master mode (ext mode) slave mode (m/s bit = ?0?) power up (pmdac bit = ?1?) po wer down (pmdac bit = ?0?) mcki pin refer to table 11 input or fixed to ?l? or ?h? externally mcko pin mcko bit = ?0?: l mcko bit = ?1?: output l bick pin input fixed to ?l? or ?h? externally lrck pin input fixed to ?l? or ?h? externally table 14. clock operation in slave mode (ext mode) for low sampling rates, dr and s/n degrade because of th e out-of-band noise. dr and s/n are improve d by using higher frequency for mcki. table 15 shows dr and s/n when the dac output is to the hp-amp. dr, s/n (bw=20khz, a-weight) mcki fs=8khz fs=16khz 256fs/384fs/512fs 56db 75db 768fs/1024fs 75db 90db table 15. relationship between mcki freque ncy and dr (and s/n) of hp-amp (2.4v)
[ak4372] ms0684-e-02 2008/12 - 24 - serial data interface the ak4372 interfaces with external system s via the sdata, bick and lrck pins . five data formats are available, selected by setting the dif2, dif1 and dif0 bits ( table 16 ). mode 0 is compatible with existing 16-bit dacs and digital filters. mode 1 is a 20-bit version of mode 0. mode 4 is a 24-bit version of mode 0. mode 2 is similar to akm adcs and many dsp serial ports. mode 3 is compatible with the i 2 s serial data protocol. in modes 2 and 3 with bick 48fs, the following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four zeros (21st to 24th bits). in all modes, the serial data is msb first and 2?s complement format. when master mode and bick=32fs(bf bit = ?0?), the ak4372 cannot be set to mode 1 mode 2 or mode 4. mode dif2 dif1 dif0 format bick figure 0 0 0 0 0: 16bit, lsb justified 32fs bick 64fs figure 17 1 0 0 1 1: 20bit, lsb justified 40fs bick 64fs figure 18 2 0 1 0 2: 24bit, msb justified 48fs bick 64fs figure 19 (default) 3 0 1 1 3: i 2 s compatible bick=32fs or 48fs bick 64fs figure 20 4 1 0 0 4: 24bit, lsb justified 48fs bick 64fs figure 18 table 16. audio data format sdata bick lrck sdata 15 14 6 5 4 bick 3 2 1 0 15 14 ( 32fs ) 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 17. mode 0 timing (lrp = bckp bits = ?0?) sdata lrck bick 19 0 19 0 mode 1 don?t care don?t care 19:msb, 0:lsb sdata mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 23 23 figure 18. mode 1, 4 timing (lrp = bckp bits = ?0?)
[ak4372] ms0684-e-02 2008/12 - 25 - lrck bick sdata 16bit don?t 0 14 15 14 15 lch rch care 14 0 15 sdata 20bit 18 19 18 19 4 1 0 don?t care 18 19 410 don?t care don?t care sdata 24bit 22 23 22 23 don?t care 22 23 don?t care 8 3 4 0 1 83 4 0 1 figure 19. mode 2 timing (lrp = bckp bits = ?0?) lrck lch rch bick don?t 0 14 15 15 care 14 0 15 19 18 19 4 1 0 don?t care 18 19 41 0 don?t care don?t care sdata 16bit sdata 20bit sdata 24bit 23 22 23 don?t care 22 23 don?t care 8 3 4 0 1 83 4 0 1 bick 6 14 15 15 14 6 15 sdata 16bit ( 32fs ) 0 5 4 321 0 54 3 2 1 0 figure 20. mode 3 timing (lrp = bckp bits = ?0?)
[ak4372] ms0684-e-02 2008/12 - 26 - digital attenuator the ak4372 has a channel-independent digita l attenuator (256 levels, 0.5db step). th is digital attenuator is placed before the d/a converter. attl/r7-0 bits set the attenuation level (0db to ? 127db or mute) for each channel ( table 17 ). at dattc bit = ?1?, attl7-0 bits control both channel?s attenuation levels. at da ttc bit = ?0?, attl7-0 bits control the left channel level and attr7-0 bits control the right channel level. attl7-0 attr7-0 attenuation ffh 0db feh ? 0.5db fdh ? 1.0db fch ? 1.5db : : 02h ? 126.5db 01h ? 127.0db 00h mute ( ? ) (default) table 17. digital volume att values the ats bit sets the transition time between set values of att7-0 bits as either 1061/fs or 7424/fs ( table 18 ). when the ats bit = ?0?, a soft transition between the set values occurs(1062 levels). it takes 1061/fs (24ms@fs=44.1khz) from ffh(0db) to 00h(mute). the atts are 00h when the pmdac bit is ?0?. when the pmdac returns to ?1?, the atts fade to their current value. the digital attenua tor is independent of the soft mute function. att speed ats 0db to mute 1 step 0 1061/fs 4/fs (default) 1 7424/fs 29/fs table 18. transition time between set values of att7-0 bits
[ak4372] ms0684-e-02 2008/12 - 27 - soft mute soft mute operation is performed in the digital domain. when the smute bit changes to ?1?, the output signal is attenuated by ? during the att_data att transition time ( table 18 ) from the current att level. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to ? after starting the operation, the attenuation is discontinued and is returned to the att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit a ttenuation ats bit att level - a nalog output gd gd (1) (2) (3) ats bit (1) figure 21. soft mute function notes: (1) att_data att transition time ( table 18 ). for example, this time is 3712lrck cycles (3712/fs) at ats bit = ?1? and att_data = ?128?(-63.5db). (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to ? after starting the operation, the attenuation is discontinued and it is returned to the att level by the same cycle.
[ak4372] ms0684-e-02 2008/12 - 28 - de-emphasis filter the ak4372 includes a digital de -emphasis filter (tc = 50/15 s), using an iir filter co rresponding to three sampling frequencies (32khz, 44.1khz and 48khz). the de-emphasi s filter is enabled by setting dem1-0 bits ( table 19 ). dem1 bit dem0 bit de-emphasis 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 19. de-emphasis filter frequency select bass boost function by controlling the bst1-0 bits, a low frequency boost signa l can be output from dac. the setting value is common for both channels ( table 20 ). bst1 bit bst0 bit boost 0 0 off (default) 0 1 min 1 0 mid 1 1 max table 20. low frequency boost select digital mixing function mono1-0 bits select the digital data mixing for the dac ( table 21 ). mono1 bit mono0 bit lch rch 0 0 l r (default) 0 1 l l 1 0 r r 1 1 (l+r)/2 (l+r)/2 table 21. mixer setting system reset the pdn pin should be held to ?l? upon power-up. the 4372 s hould be reset by bringing the pdn pin ?l? for 150ns or more. all of the internal register values are initialized by the system reset. after exiting reset, vcom, dac, hpl, hpr, lout and rout switch to the power-down state. the contents of the control register are maintained until the reset is completed. the dac exits reset and power down states by mcki after the pmdac bit is changed to ?1?. the dac is in power-down mode until mcki is input.
[ak4372] ms0684-e-02 2008/12 - 29 - headphone output (hpl, hpr pins) the power supply voltage for the headphone-amp is supp lied from the avdd pin and is centered on the mutet voltage. the headphone-amp output load resistance is 16 (min). when the muten bit is ?1? at pmhpl=pmhpr= ?1?, the common voltage rises to 0.475 x avdd. when the muten bit is ?0?, the common voltage of the headphone-amp falls and the outputs (hpl and hpr pins) go to vss1. t r : rise time up to vcom/2 70k x c (typ) t f : fall time down to vcom/2 60k x c (typ) table 22. headphone-amp rise/fall time [example] : capacitor between the mutet pin and ground = 1 f: rise time up to vcom/2: t r = 70k x 1 = 70ms(typ). fall time down to vcom/2: t f = 60k x 1 = 60ms(typ). when the pmhpl and pmhpr bits are ?0?, the headphone-amp is powered-down, and the outputs (hpl and hpr pins) go to vss1. muten bit pmhpl/r bit hpl/r pin (1) (2) (4) (3) t r t f vcom/2 vcom figure 22. power-up/power-down timing for the headphone-amp (1) headphone-amp power-up (pmhpl and pmhpr b its = ?1?). the outputs are still at vss1. (2) headphone-amp common voltage rises up (muten bit = ?1?). common voltage of the headphone-amp is rising. this rise time depends on the capacitor value connected with the mutet pin. the rise time up to vcom/2 is t r = 70k x c(typ) when the capacitor value on mutet pin is ?c?. (3) headphone-amp common voltage falls down (muten bit = ?0?). common voltage of the headphone-amp is falling to vss1. this fall time depends on the capacitor value connect ed with the mutet pin. the fall time down to vcom/2 is t f = 60k x c(typ) when the capacito r value on the mutet pin is ?c?. (4) headphone-amp power-down (pmhpl, pmhpr bits = ?0?). the outputs are at vss1. if the power supply is switched off or the headphone-amp is powered-down before the co mmon voltage settles to vss1, some pop noise may occur.
[ak4372] ms0684-e-02 2008/12 - 30 - < external circuit of headphone-amp > the cut-off frequency of the headphone-amp output depe nds on the external resistor and capacitor used. table 23 shows the cut off frequency and the output power for various re sistor/capacitor combinations. the headphone impedance r l is 16 . output powers are shown at avdd = 2.4, 3.0 and 3.3v. the output voltage of the headphone-amp is 0.48 x avdd (vpp) @ ? 3dbfs. ak4372 hp-amp 16 headphone r c figure 23. external circuit example of headphone output power [mw] r [ ] c [ f] fc [hz] boost=off fc [hz] boost=min 2.4v 3.0v 3.3v 220 45 17 0 100 100 43 21 33 40 100 70 28 6.8 47 149 78 10 16 20 100 50 19 16 47 106 47 5 8 10 table 23. relationship of external circ uit, output power and frequency response < wired or with external headphone-amp > when pmvcm=pmhpl=pmhpr bits = ?0? and hpz bit = ?1?, headphone-amp is powered-down and hpl/r pins are pulled-down to vss1 by 200k (typ). in this setting, it is able to connect headphone-amp of ak4372 and external single supply headphone-amp by ?wired or?. pmvcm pmhpl/r hpmtn hpz mode hpl/r pins x 0 x 0 power-down & mute vss1 (default) 0 0 x 1 power-down pull-down by 200k 1 1 0 x mute vss1 1 1 1 x normal operation normal operation table 24. hp-amp mode setting (x: don?t care) hpl pin hpr pin headphone ak4372 anothe r hp-amp figure 24. wired or with external hp-amp
[ak4372] ms0684-e-02 2008/12 - 31 - < analog mixing circuit for headphone output > dalhl, linhl, rinhl and minhl bits control each path switch of the hpl output . darhr, linhr, rinhr and minhr bits control each path switch of the hpr output. when lhm bit = ?0?, hpg1-0 bits = ?00? (r 1h = r 2h = r dh = 100k) and atth4-0 bits = ?00h?(0db), the mixing gain is +0.95db(typ). when hpg1-0 bit = ?01? (r dh = 50k), the mixing gain of dac path is +6.95db(typ). when hpg1-0 bit = ?10? (r dh = 25k), the mixing gain of dac path is +12.95db(typ). when lhm bit is ?1?, lin and rin signals are output from the hpl/r pins as (l+r)/2 respectively. when ldif=ldifh=linl=rinr bits = ?1?, the lin and rin pins becomes in+ and in ? pins, respectively. the in+ and in ? pins can be used as full-differential mono line input for analog mixing for headphone-amp. in this case, linhl, rinhl, linhr and rinhr bits should be ?0?. if the path is off and the signal is input to the input pin, th e input pin should be biased to a voltage equivalent to vcom voltage (= 0.475 x avdd) externally. figure 51 shows the external bias circuit example. ? + hpl pin hp-amp 1.11r h r dh dalhl bit ? + 100k(typ) r h min pin minhl bit r 2h dac lch rin pin r 1h rinhl bit lin pin r 1h linhl bit figure 27 100k(typ) ldifh bit ? + hpr pin hp-amp 1.11r h r dh darhr bit ? + 100k(typ) r h min pin minhr bit r 2h dac rch rin pin r 1h rinhr bit lin pin r 1h linhr bit figure 27 100k(typ) ldifh bit figure 25. summation circuit for hpl/r output
[ak4372] ms0684-e-02 2008/12 - 32 - headphone output volume hpl/hpr volume is controlled by atth4-0 bits when hmute bit = ?0? (+12db ? 51db or +6db ? 57db or 0db ? 63db, 1.5db or 3db step, table 25 ) hmute atth4-0 hpg1-0 bits = ?10? (dac only) hpg1-0 bits = ?01? (dac only) hpg1-0 bits = ?00? step 00h +12db +6db 0db (default) 01h +10.5db +4.5db ? 1.5db 02h +9db +3db ? 3db 03h +7.5db +1.5db ? 4.5db : : : : 1.5db 12h ? 15db ? 21db ? 27db 13h ? 16.5db ? 22.5db ? 28.5db 14h ? 18db ? 24db ? 30db 15h ? 21db ? 27db ? 33db 16h ? 24db ? 30db ? 36db : : : : 3db 1dh ? 45db ? 51db ? 57db 1eh ? 48db ? 54db ? 60db 0 1fh ? 51db ? 57db ? 63db 1 x mute mute mute table 25. hpl/hpr volume att values (x: don?t care)
[ak4372] ms0684-e-02 2008/12 - 33 - stereo line output (lout, rout pins) the common voltage is 0.475 x avdd. the load resistance is 10k (min). when the pmlo bit is ?1?, the stereo line output is powered-up. dall, linl, rinl and minl bits control each path switch of lout. darr, linr, rinr and minr bits control each path switch of r out. when lm bit = ?0?, log bit = ?0? (r 1l = r 2l = r dl = 100k) and atts3-0 bits is ?0fh?(0db), the mixing gain is 0db(typ) for all paths. when the log bit = ?1?(r dl = 50k), the dac path gain is +6db. when lm bit = ?1?, lin and rin signals are output from lout/rout pins as (l+r)/2 respectively. if the path is off and the signal is input to the input pin, th e input pin should be biased to a voltage equivalent to vcom voltage (= 0.475 x avdd) externally. figure 51 shows the external bias circuit example. ? + lout pin r l r dl dall bit ? + 100k(typ) r l min pin r 2l minl bit dac lch rin pin r 1l rinl bit lin pin r 1l linl bit ? + rout pin r l r dl darr bit ? + 100k(typ) r l min pin r 2l minr bit dac rch rin pin r 1l rinr bit lin pin r 1l linr bit figure 26. summation circuit for stereo line output
[ak4372] ms0684-e-02 2008/12 - 34 - < analog mixing circuit of full-differential mono input > when ldif=linl=rinr bits = ?1?, th e lin and rin pins becomes in+ and in ? pins, respectively. the in ? and in+ pins can be used as full-differential mono line input for an alog mixing of lout/rout pins. it is not available to mix with other signal source for lout/rout outputs. if the path is off and the signal is input to the input pin, th e input pin should be biased to a voltage equivalent to vcom voltage (= 0.475 x avdd) externally. figure 51 shows the external bias circuit example. ? + lout pin in ? p in r l 100k(typ) r 2l linl bit ldif bit ? + 100k(typ) r l ? + rout pin r l r l in+ pin r 2l rinr bit ? + 100k(typ) hpl/r pins ldifh bit figure 25 figure 27. summation circuit for stereo line output (full-differential input) v stereo line output (lout/rout pins) volume lout/rout volume is controlled by atts3-0 bits when lmute bit = ?0? (+6db ? 24db or 0db ? 30db, 2db step, table 26 ). pop noise occurs when atts3-0 bits are changed. lmute atts3-0 log bit = ?1? (dac only) log bit = ?0? fh +6db 0db eh +4db ? 2db dh +2db ? 4db ch 0db ? 6db : : : 1h ? 22db ? 28db 0 0h ? 24db ? 30db 1 x mute mute (default) table 26. lout/rout volume att values (x: don?t care)
[ak4372] ms0684-e-02 2008/12 - 35 - power-up/down sequence (ext mode) 1) dac hp-amp power supply pdn pin pmvcm bit clock input (3) sdti pin pmdac bit dac internal state pd normal operation hpl/r pin pmhpl, pmhpr bits (6) a ttl7-0 a ttr7-0 bits 00h(mute) ffh(0db) (8) gd (9) 1061/fs pd normal operation 00h(mute) ffh(0db) (8) (9) (6) (7) (8) (9) don?t care don?t care (7) (8) (9) 00h(mute) don?t care (10) don?t care (1) >150ns (2) >0s pd (5) >2ms muten bit dalhl, darhr bits (4) >0s (4) >0s (5) >2ms figure 28. power-up/down sequence of dac and hp-amp (don?t care: except hi-z) (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. (2) pmvcm and pmdac bits should be changed to ?1? after the pdn pin is set to ?h?. (3) external clocks (mcki, bick, lrck) are needed to operate the dac. when the pmdac bit = ?0?, these clocks can be stopped. the headphone-amp can operate without these clocks. (4) dalhl and darhr bits should be changed to ?1? after pmvcm and pmdac bit is changed to ?1?. (5) pmhpl, pmhpr and muten bits should be changed to ?1? at least 2ms (in case external capacitance at vcom pin is 2.2 f) after the dalhl and darhr bits are changed to ?1? (6) rise time of the headphone-amp is determined by an exte rnal capacitor (c) of the mutet pin. the rise time up to vcom/2 is t r = 70k x c(typ). when c=1 f, t r = 70ms(typ). (7) fall time of the headphone-amp is determined by an exte rnal capacitor (c) of the mu tet pin. the fall time down to vcom/2 is t f = 60k x c(typ). when c=1 f, t f = 60ms(typ). pmhpl and pmhpr bits should be changed to ?0? after the hpl and hpr pins settle to vss1. after that, the dalhl and darhr bits should be changed to ?0?. (8) analog output corresponding to the digital input ha s a group delay (gd) of 22/fs(=499s@fs=44.1khz). (9) the ats bit sets transition time of digital atte nuator. default value is 1061/fs(=24ms@fs=44.1khz). (10) the power supply should be switched off after the hea dphone-amp is powered down (hpl/r pins become ?l?). when avdd and dvdd are supplied separately, dvdd should be powered-down at the same time or later than avdd.
[ak4372] ms0684-e-02 2008/12 - 36 - 2) dac lineout power supply pdn pin pmvcm bit clock input (5) sdti pin pmdac bit dac internal state pd(power-down) normal operation pmlo bit a ttl/r7-0 bits 00h(mute) ffh(0db) lout/rout pins (6) lmute, a tts3-0 bits 10h(mute) 0fh(0db) (7) gd (8) 1061/fs (hi-z) pd normal operation 00h(mute) ffh(0db) (hi-z) (7) (8) (6) (6) (7) (8) don?t care don?t care don?t care (1) >150ns (2) >0s (4) >0s dall, darr bits (3) >0s figure 29. power-up/down sequence of dac and lout/rout (don?t care: except hi-z) (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. (2) pmvcm bit should be changed to ?1? after the pdn pin is set to ?h?. (3) dall and darr bits should be changed to ?1? after the pmvcm bit is changed to ?1?. (4) pmdac and pmlo bits should be changed to ?1? after dall and darr bits is changed to ?1?. (5) external clocks (mcki, bick, lrck) are needed to operate the dac. when the pmdac bit = ?0?, these clocks can be stopped. the lout/rout buffer can operate without these clocks. (6) when the pmlo bit is changed, pop noise is output from lout/rout pins. (7) analog output corresponding to the digital input has a group delay (gd) of 22/fs(=499 s@fs=44.1khz). (8) the ats bit sets the transition time of the digital attenuator. default value is 1061/fs(=24ms@fs=44.1khz).
[ak4372] ms0684-e-02 2008/12 - 37 - 3) lin/rin/min hp-amp power supply pdn pin pmvcm bit hpl/r pins (6) (6) (7) lin/rin/min pins (4) (hi-z) (hi-z) pmhpl/r bits don?t care (1) >150ns (2) >0s muten bit linhl, minhl, rinhr, minhr bits (3) >0s (5) >2ms (5) >2ms figure 30. power-up/down sequence of lin/rin/min and hp-amp (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. mcki, bick and lrck can be stopped when dac is not used. (2) pmvcm bit should be changed to ?1? after the pdn pin is set to ?h?. (3) linhl, minhl, rinhr and minhr bits should be changed to ?1? after pmvcm bit is changed to ?1?. (4) when linhl, minhl, rinhr or minhr bit is changed to ?1?, the lin, rin or min pin is biased to 0.475 x avdd. (5) pmhpl, pmhpr and muten bits should be changed to ?1? at least 2ms (in case external capacitance at the vcom pin is 2.2 f) after linhl, minhl, rinhr and minhr bits are changed to ?1?. (6) rise time of the headphone-amp is determined by an exte rnal capacitor (c) of the mutet pin. the rise time up to vcom/2 is t r = 70k x c(typ). when c=1 f, t r = 70ms(typ). (7) fall time of the headphone-amp is determined by an exte rnal capacitor (c) of the mu tet pin. the fall time down to vcom/2 is t f = 60k x c(typ). when c=1 f, t f = 60ms(typ). pmhpl and pmhpr bits should be changed to ?0? after the hpl and hpr pins settle to vss1. after that, the linhl, minhl, rinhr and minhr bits should be changed to ?0?.
[ak4372] ms0684-e-02 2008/12 - 38 - 4) lin/rin/min lineout power supply pdn pin pmvcm bit lout/rout pins (6) lmute, a tts3-0 bits 10h(mute) 0fh(0db) (hi-z) (6) (6) lin/rin/min pins (4) (hi-z) (hi-z) pmlo bit don?t care (1) >150ns (2) >0s linl, minl, rinr, minr bits (3) >0s (5) >2ms (5) >2ms (hi-z) figure 31. power-up/down sequence of lin1/rin1/lin2/rin2/lin3/rin3 and lineout (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. mcki, bick and lrck can be stopped when dac is not used. (2) pmvcm bit should be changed to ?1? after the pdn pin is set to ?h?. (3) linl, minl, rinr and minr bits should be changed to ?1? after pmvcm bit is changed to ?1?. (4) when linl, minl, rinr or minr bit is changed to ?1?, the lin, rin or min pin is biased to 0.475 x avdd. (5) pmlo bit should be changed to ?1? at least 2ms (in case external capacitance at vcom pin is 2.2 f) after linl, minl, rinr and minr bits are changed to ?1?. (6) when the pmlo bit is changed, pop noise is output from the lout/rout pins.
[ak4372] ms0684-e-02 2008/12 - 39 - ? power-up/down sequence (pll slave mode) 1) dac hp-amp power supply pdn pin pmvcm, pmpll, pmdac , mck o bits mcki pin (3) sdti pin dac internal state pd normal operation hpl/r pin pmhpl, pmhpr bits (8) a ttl7-0 a ttr7-0 bits 00h(mute) ffh(0db) (10) gd (11) 1061/fs pd normal operation 00h(mute) ffh(0db) (10) (11) (8) (9) (10 ) (11) don?t care don?t care (9 ) (10) (11) 00h(mute) don?t care (12) (1) >150ns (2) >0s pd (7) >2ms mu ten bit dalhl, darhr bits (6) >0s (6) >0s (7) >2ms mcko pin don?t care bick, lrck pins don?t care unstable unstable don?t care unstable (4) ~20ms (5) (4) ~20ms unstable unstable unstable don?t care unstable don?t care (5) figure 32. power-up/down sequence of dac and hp-amp (don?t care: except hi-z) (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. (2) pmvcm, pmpll, pmdac and mcko bits should be changed to ?1? after the pdn pin goes ?h?. (3) the pll operation is executed when the system clock is input to the mcki pin. (4) the pll lock time is referred to table 4 . after the pll is locked, the mc ko pin outputs the master clock. (5) the clocks (bick, lrck) generated by mcko are needed to operate the dac. when th e pmdac bit = ?0?, these clocks can be stopped. the headphone-amp can operate without these clocks. (6) dalhl and darhr bits should be changed to ?1? after the pll is locked. (7) pmhpl, pmhpr and muten bits should be changed to ?1? at least 2ms (in case external capacitance at vcom pin is 2.2 f) after the dalhl and darhr bits are changed to ?1?. (8) rise time of the headphone-amp is determined by an exte rnal capacitor (c) of the mutet pin. the rise time up to vcom/2 is t r = 70k x c(typ). when c=1 f, t r = 70ms(typ). (9) fall time of the headphone-amp is determined by an exte rnal capacitor (c) of the mu tet pin. the fall time down to vcom/2 is t f = 60k x c(typ). when c=1 f, t f = 60ms(typ). pmhpl and pmhpr bits should be changed to ?0? after hpl and hpr pins go to hvss. after that, the dalhl/darhr bits should be changed to ?0?. (10) analog output corresponding to the digital input has a group delay (gd) of 22/fs(=499 s@fs=44.1khz). (11) the ats bit sets transition time of digital atte nuator. default value is 1061/fs(=24ms@fs=44.1khz). (12) the power supply should be switched off after the hea dphone-amp is powered down (hpl/r pins become ?l?). when avdd and dvdd are supplied separately, dvdd should be powered-down at the same time or after avdd.
[ak4372] ms0684-e-02 2008/12 - 40 - 2) dac lineout mcko pin bick, lrck pins don?t care power supply pdn pin pmvcm, pmpll, pmdac, mcko bits mcki pin (5) sdti pin dac internal state pd normal operation pmlo bit a ttl/r7-0 bits 00h(mute) ffh(0db) lout/rout pins (8) lmute, a tts3-0 bits 10h(mute) 0fh(0db) (9) gd (10) 1061/fs (hi-z) pd normal operation 00h(mute) ffh(0db) (h i-z) (9) (10) (8) (8) (9 ) (10) don?t care don?t care (1) >150ns (2)>0s (7) >0s dall, darr bits (6) >0s unstable unstable don?t care unstable unstable (4) ~20ms (3) don?t care unstable unstable unstable unstable ( 7) >0s (4) ~20ms (6) >0s (5) figure 33. power-up/down sequence of dac and lout/rout (don?t care: except hi-z) (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. (2) pmvcm, pmpll, pmdac and mcko bits should be changed to ?1? after the pdn pin goes ?h?. (3) the pll operation is executed when the system clock is input to the mcki pin. (4) the pll lock time is referred to table 4 . after the pll is locked, the mc ko pin outputs the master clock. (5) the clocks (bick, lrck) generated by mcko are needed to operate the dac. when th e pmdac bit = ?0?, these clocks can be stopped. the lout/rout bu ffer can operate without these clocks. (6) dall and darr bits should be changed to ?1? after the pll is locked (7) pmlo bit is changed to ?1?. (8) when the pmlo bit is changed, pop noise is output from lout/rout pins. (9) analog output corresponding to the digital input has group delay (gd) of 22fs(=499 s@fs=44.1khz). (10) the ats bit sets the transition time of the digital a ttenuator. default value is 1061/fs(=24ms@fs=44.1khz).
[ak4372] ms0684-e-02 2008/12 - 41 - 3) lin/rin/min hp-amp power supply pdn pin pmvcm bit hpl/r pins (6) (6) (7) lin/rin/min pins (4) (hi-z) (hi-z) pmhpl/r bits don?t care (1) >150ns (2) >0s muten bit linhl, minhl, rinhr, minhr bits (3) >0s (5) >2ms (5) >2ms figure 34. power-up/down sequence of lin/rin/min and hp-amp (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. mcki, bick and lrck can be stopped when dac is not used. (2) pmvcm bit should be changed to ?1? after the pdn pin is set to ?h?. (3) linhl, minhl, rinhr and minhr bits should be changed to ?1? after pmvcm bit is changed to ?1?. (4) when linhl, minhl, rinhr or minhr bit is changed to ?1?, the lin, rin or min pin is biased to 0.475 x avdd. (5) pmhpl, pmhpr and muten bits should be changed to ?1? at least 2ms (in case external capacitance at the vcom pin is 2.2 f) after linhl, minhl, rinhr and minhr bits are changed to ?1?. (6) rise time of the headphone-amp is determined by an exte rnal capacitor (c) of the mutet pin. the rise time up to vcom/2 is t r = 70k x c(typ). when c=1 f, t r = 70ms(typ). (7) fall time of the headphone-amp is determined by an exte rnal capacitor (c) of the mu tet pin. the fall time down to vcom/2 is t f = 60k x c(typ). when c=1 f, t f = 60ms(typ). pmhpl and pmhpr bits should be changed to ?0? after the hpl and hpr pins settle to vss1. after that, the linhl, minhl, rinhr and minhr bits should be changed to ?0?.
[ak4372] ms0684-e-02 2008/12 - 42 - 4) lin/rin/min lineout power supply pdn pin pmvcm bit lout/rout pins (6) lmute, a tts3-0 bits 10h(mute) 0fh(0db) (hi-z) (6) (6) lin/rin/min pins (4) (hi-z) (hi-z) pmlo bit don?t care (1) >150ns (2) >0s linl, minl, rinr, minr bits (3) >0s (5) >2ms (5) >2ms (hi-z) figure 35. power-up/down sequence of lin1/rin1/lin2/rin2/lin3/rin3 and lineout (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. mcki, bick and lrck can be stopped when dac is not used. (2) pmvcm bit should be changed to ?1? after the pdn pin is set to ?h?. (3) linl, minl, rinr and minr bits should be changed to ?1? after pmvcm bit is changed to ?1?. (4) when linl, minl, rinr or minr bit is changed to ?1?, the lin, rin or min pin is biased to 0.475 x avdd. (5) pmlo bit should be changed to ?1? at least 2ms (in case external capacitance at the vcom pin is 2.2 f) after linl, minl, rinr and minr bits are changed to ?1?. (6) when the pmlo bit is changed, pop noise is output from the lout/rout pins.
[ak4372] ms0684-e-02 2008/12 - 43 - ? power-up/down sequence (pll master mode) 1) dac hp-amp power supply pdn pin m/s, pmvcm, pmpll, pmdac, mcko bits mcki pin (3) sdti pin dac internal state pd normal operation hpl/r pin pmhpl, pmhpr bits (7) a ttl7-0 a ttr7-0 bits 00h(mute) ffh(0db) (9) gd (10) 1061/fs pd normal operation 00h(mute) ffh(0db) (9 ) (10) (7) (8) (9) (10) don?t care don?t care (8) (9) (10) 00h(mute) don?t care (11) (1) >150ns (2) >0 pd (6) >2ms mu ten bi t dalhl, darhr bits (5) >0 (5) >0 (6) >2ms mcko pin don?t care bick, lrck pins don?t care unstable unstable don?t care unstable (4) ~20ms (4) ~20ms unstable unstable don?t care unstable don?t care ?l? unstable figure 36 power-up/down sequence of dac and hp-amp (don?t care: except hi-z) (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. (2) pmvcm, pmpll, pmdac, mcko and m/s bits should be changed to ?1? after the pdn pin goes ?h?. (3) the pll operation is executed when the system clock is input to the mcki pin. (4) the pll lock time is referred to table 4 . after the pll is locked, each clock is output from bick, lrck and mcko pins. (5) dalhl and darhr bits should be changed to ?1? after the pll is locked. (6) pmhpl, pmhpr and muten bits should be changed to ?1? at least 2ms (in case external capacitance at vcom pin is 2.2 f) after the dalhl and darhr bits are changed to ?1?. (7) rise time of the headphone-amp is determined by an exte rnal capacitor (c) of the mutet pin. the rise time up to vcom/2 is t r = 70k x c(typ). when c=1 f, t r = 70ms(typ). (8) fall time of the headphone-amp is determined by an exte rnal capacitor (c) of the mu tet pin. the fall time down to vcom/2 is t f = 60k x c(typ). when c=1 f, t f = 60ms(typ). pmhpl and pmhpr bits should be changed to ?0? after hpl and hpr pins go to hvss. after that, the dalhl/darhr bits should be changed to ?0?. (9) analog output corresponding to the digital input has group delay (gd) of 22/fs(=499 s@fs=44.1khz). (10) the ats bit sets transition time of digital atte nuator. default value is 1061/fs(=24ms@fs=44.1khz). (11) the power supply should be switched off after the hea dphone-amp is powered down (hpl/r pins become ?l?). when avdd and dvdd are supplied separately, dvdd should be powered-down at the same time or after avdd.
[ak4372] ms0684-e-02 2008/12 - 44 - 2) dac lineout mcko pin bick, lrck pins don?t care power supply pdn pin m/s, pmvcm, pmpll, pmdac, mcko bits mcki pin sdti pin dac internal st a t e pd normal operation pmlo bit a ttl/r7-0 bits 00h(mute) ffh(0db) lout/rout pins (7) lmute, a tts3-0 bits 10h(mute) 0fh(0db) (8) gd (9) 1061/fs (hi-z) pd normal operation 00h(mute) ffh(0db) (h i-z) (8) (9) (7) (8) (8) (9) don?t care don?t care (1) >150ns (2) >0 (6) >0 dall, darr bits (5) >0 unstable ?l? don?t care unstable unstable (4) ~20ms (3) don?t care unstable unstable unstable unstable (6) >0 (4) ~20ms (5) >0 figure 37. power-up/down sequence of dac and lout/rout(don?t care: except hi-z) (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. (2) pmvcm, pmpll, pmdac, mcko and m/s bits should be changed to ?1? after the pdn pin goes ?h?. (3) the pll operation is executed when the system clock is input to the mcki pin. (4) the pll lock time is referred to table 4 . after the pll is locked, each clock is output from bick, lrck and mcko pins. (5) dall and darr bits should be changed to ?1? after the pll is locked. (6) pmlo bit is changed to ?1?. (7) when the pmlo bit is changed, pop noise is output from lout/rout pins. (8) analog output corresponding to the digital input has group delay (gd) of 22fs(=499 s@fs=44.1khz). (9) the ats bit sets the transition time of the digital attenuator. default value is 1061/fs(=24ms@fs=44.1khz).
[ak4372] ms0684-e-02 2008/12 - 45 - 3) lin/rin/min hp-amp power supply pdn pin pmvcm bit hpl/r pins (6) (6) (7) lin/rin/min pins (4) (hi-z) (hi-z) pmhpl/r bits don?t care (1) >150ns (2) >0s muten bit linhl, minhl, rinhr, minhr bits (3) >0s (5) >2ms (5) >2ms figure 38. power-up/down sequence of lin/rin/min and hp-amp (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. mcki, bick and lrck can be stopped when dac is not used. (2) pmvcm bit should be changed to ?1? after the pdn pin is set to ?h?. (3) linhl, minhl, rinhr and minhr bits should be changed to ?1? after pmvcm bit is changed to ?1?. (4) when linhl, minhl, rinhr or minhr bit is changed to ?1?, the lin, rin or min pin is biased to 0.475 x avdd. (5) pmhpl, pmhpr and muten bits should be changed to ?1? at least 2ms (in case external capacitance at the vcom pin is 2.2 f) after linhl, minhl, rinhr and minhr bits are changed to ?1?. (6) rise time of the headphone-amp is determined by an exte rnal capacitor (c) of the mutet pin. the rise time up to vcom/2 is t r = 70k x c(typ). when c=1 f, t r = 70ms(typ). (7) fall time of the headphone-amp is determined by an exte rnal capacitor (c) of the mu tet pin. the fall time down to vcom/2 is t f = 60k x c(typ). when c=1 f, t f = 60ms(typ). pmhpl and pmhpr bits should be changed to ?0? after the hpl and hpr pins settle to vss1. after that, the linhl, minhl, rinhr and minhr bits should be changed to ?0?.
[ak4372] ms0684-e-02 2008/12 - 46 - 4) lin/rin/min lineout power supply pdn pin pmvcm bit lout/rout pins (6) lmute, a tts3-0 bits 10h(mute) 0fh(0db) (hi-z) (6) (6) lin/rin/min pins (4) (hi-z) (hi-z) pmlo bit don?t care (1) >150ns (2) >0s linl, minl, rinr, minr bits (3) >0s (5) >2ms (5) >2ms (hi-z) figure 39. power-up/down sequence of lin1/rin1/lin2/rin2/lin3/rin3 and lineout (1) when avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. the pdn pin should be set to ?h? at least 150ns after power is supplied. mcki, bick and lrck can be stopped when dac is not used. (2) pmvcm bit should be changed to ?1? after the pdn pin is set to ?h?. (3) linl, minl, rinr and minr bits should be changed to ?1? after pmvcm bit is changed to ?1?. (4) when linl, minl, rinr or minr bit is changed to ?1?, the lin, rin or min pin is biased to 0.475 x avdd. (5) pmlo bit should be changed to ?1? at least 2ms (in case external capacitance at the vcom pin is 2.2 f) after linl, minl, rinr and minr bits are changed to ?1?. (6) when the pmlo bit is changed, pop noise is output from the lout/rout pins.
[ak4372] ms0684-e-02 2008/12 - 47 - serial control interface (1) 3-wire serial control mode (i2c pin = ?l?) internal registers may be written to via the 3-wire p interface pins (csn, cclk and cdti). the data on this interface consists of the chip address (2-bits, fixed to ?01?), read/wr ite (1-bit, fixed to ?1?, write only), register address (msb first, 5-bits) and control data (msb first, 8-bits). address and data are clocked in on the rising edge of cclk. for write operations, the data is latched after a low-to-high transition of the 16th cclk. csn should be set to ?h? once after 16 cclks for each address. the clock speed of cclk is 5mhz(max). the value of the internal re gisters is initialized at the pdn pin = ?l?. csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdti c1 c0 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w clock, ?h? or ?l? clock, ?h? or ?l? ?h? or ?l? ?h? or ?l? c1-c0: chip address (fixed to ?01?) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 40. 3-wire serial control i/f timing
[ak4372] ms0684-e-02 2008/12 - 48 - (2) i 2 c-bus control mode (i2c pin = ?h?) the ak4372 supports fast-mode i 2 c-bus (max: 400khz, version 1.0). (2)-1. write operations figure 41 shows the data transfer sequence for the i 2 c-bus mode. all commands are preceded by start condition. a high to low transition on the sda line while scl is high indicates start condition ( figure 47 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant six bits of the slave address are fixed as ?001000?. the next bit is cad0 (device address bit). this bit identifies the specific device on the bus. the hard-wired input pin (cad0 pin) sets this device address bit ( figure 42 ). if the slave address matches that of the ak4372, the ak4372 generates an acknowledgement and the operation is executed. the master must generate the acknowledge-relate d clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 48 ). a r/w bit value of ?1? indicates that th e read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4372. the format is msb first, and those most significant 3-bits are fixed to zeros ( figure 43 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 44 ). the ak4372 generates an acknowledgement after each byte is received. a data transfer is always terminated by stop condition generated by the master. a low to high transition on the sda line while scl is high defines stop condition ( figure 47 ). the ak4372 can perform more than one byte write operati on per sequence. after receiving the third byte the ak4372 generates an acknowledgement and awaits the next data. th e master can transmit more than one byte instead of terminating the write cycle after the first data byte is tran sferred. after receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 13h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. the high or low state of the data line can only change when the cl ock signal on the scl line is low( figure 49 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 41. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 0 cad0 r/w (those cad0 should match with cad0 pin) figure 42. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 43. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 44. byte structure after the second byte
[ak4372] ms0684-e-02 2008/12 - 49 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the ak4372. after a transmission of data, the master can read the next address?s data by generating an acknowle dge instead of terminating the writing cy cle after receiving the first data word. after receiving each data packet the inte rnal 5-bit address counter is increm ented by one, and the next data is automatically taken into the next address. if the address exceeds 13h prior to generating a stop condition, the address counter will ?roll over? to 00h and th e previous data will be overwritten. the ak4372 supports two basic read operations: current address read and random address read. (2)-2-1. current address read the ak4372 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) were to address ?n ?, the next current read operation would access data from the address ?n+1?. after receiving the sl ave address with r/w bit ?1 ?, the ak4372 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter, and increments the internal address counter by 1. if the master does not generate an acknow ledgement but instead gene rates stop condition, the ak4372 ceases transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) a c k p s t o p data(n) figure 45. current address read (2)-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. th e master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave addr ess with the r/w bit ?1?. the ak4372 then generates an acknowledgement, 1 byte of data and increments the internal address counter by 1. if the master does not generate an acknowledgement but instead generates stop condition, th e ak4372 ceases transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k a c k figure 46. random address read
[ak4372] ms0684-e-02 2008/12 - 50 - scl sda stop condition start condition s p figure 47. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 48. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 49. bit transfer on the i 2 c-bus
[ak4372] ms0684-e-02 2008/12 - 51 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 0 0 pmpll pmlo muten pmhpr pmhpl pmdac pmvcm 01h pll control fs3 fs2 fs1 fs0 pll3 pll2 pll1 pll0 02h clock control pll4 0 m/s mckac bf ps0 ps1 mcko 03h mode control 0 0 mono1 mono0 bckp lrp dif2 dif1 dif0 04h mode control 1 ats dattc lmute smute bst1 bst0 dem1 dem0 05h dac lch att attl7 attl6 attl5 attl4 a ttl3 attl2 attl1 attl0 06h dac rch att attr7 attr6 attr5 attr4 a ttr3 attr2 attr1 attr0 07h headphone out select 0 hpg1 hpg0 minhr minhl rinhr linhl darhr dalhl 08h lineout select 0 0 log minr minl rinr linl darr dall 09h lineout att 0 0 0 0 atts3 atts2 atts1 atts0 0ah reserved 0 0 0 0 0 0 0 0 0bh reserved 0 0 0 0 0 0 0 0 0ch reserved 0 0 0 0 0 0 0 0 0dh headphone out select 1 0 0 0 0 0 0 linhr rinhl 0eh headphone att 0 hpz hmute atth4 atth3 atth2 atth1 atth0 0fh lineout select 1 0 0 0 0 0 0 linr rinl 10h mono mixing 0 0 0 0 0 0 lm lhm 11h differential select 0 0 0 0 0 0 ldifh ldif 12h reserved 0 0 0 0 0 0 0 0 13h reserved 0 0 0 1 0 0 0 0 all registers inhibit writ ing at pdn pin = ?l?. pdn pin = ?l? resets the registers to their default values. for addresses from 14h to 1fh, data must not be written. unused bits indicated by ?0 ? must contain a ?0? value. unused bits indicated by ?1 ? must contain a ?1? value.
[ak4372] ms0684-e-02 2008/12 - 52 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 0 0 pmpll pmlo muten pmhpr pmhpl pmdac pmvcm r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmvcm: power management for vcom block 0: power off (default) 1: power on pmdac: power management for dac blocks 0: power off (default) 1: power on when the pmdac bit is changed from ?0? to ?1?, the dac is powered-up to the current register values (att value, sampling rate, etc). pmhpl: power management for the left channel of the headphone-amp 0: power off (default). the hpl pin settles to vss1(0v). 1: power on pmhpr: power management for the right channel of the headphone-amp 0: power off (default). the hpr pin settles to vss1(0v). 1: power on muten: headphone amp mute control 0: mute (default). the hpl and hpr pins settles to vss1(0v). 1: normal operation. hpl and hpr pins go to 0.475 x avdd. pmlo: power management for stereo output 0: power off (default) lout/r out pins change to hi-z. 1: power on pmpll: power management for pll 0: power off: ext mode (default) 1: power on: pll mode each block can be powered-down respectiv ely by writing ?0? in each bit of this address. wh en the pdn pin is ?l?, all blocks are powered-down regardless of setting of this address. in this case, register is initialized to the default value. when pmvcm, pmdac, pmhpl, pmhp r, pmlo, pmmo, pmpll and mcko bits are ?0?, all blocks are powered-down. the register values rema in unchanged. power supply current is 20 a(typ) in this case. for fully shut down (typ. 1 a), the pdn pin should be ?l?.
[ak4372] ms0684-e-02 2008/12 - 53 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h pll control fs3 fs2 fs1 fs0 pll3 pll2 pll1 pll0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 0 0 0 fs3-0: select sampling frequency pll mode: table 5 ext mode: table 11 pll4-0: select pll reference clock pll mode: table 3 ext mode: pll4-0 bits are disabled (pll4 bit is d7 bit of 02h.) addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h clock control pll4 0 m/s mckac bf ps0 ps1 mcko r/w r/w rd r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 mcko: control of mcko signal 0: disable (default) 1: enable ps1-0: mcko frequency pll mode: table 9 ext mode: table 12 bf: bick period setting in master mode. in slave mode, this bit is ignored. 0: 32fs (default) 1: 64fs mckac: mcki input mode select 0: cmos input (default) 1: ac coupling input m/s: select master/slave mode 0: slave mode (default) 1: master mode pll4-0: select pll reference clock pll3-0 bits are d3-0 bits of 01h.
[ak4372] ms0684-e-02 2008/12 - 54 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h mode control 0 0 mono1 mono0 bckp lrp dif2 dif1 dif0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 dif2-0: audio data interface format select ( table 16 ) default: ?010? (mode 2) lrp: lrck polarity select in slave mode 0: normal (default) 1: invert bckp: bick polarity select in slave mode 0: normal (default) 1: invert mono1-0: digital mixing select ( table 21 ) default: ?00? (lr) addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h mode control 1 ats dattc lmute smute bst1 bst0 dem1 dem0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 1 0 0 0 0 1 dem1-0: de-emphasis filter frequency select ( table 19 ) default: ?01? (off) bst1-0: low frequency boost function select ( table 20 ) default: ?00? (off) smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted lmute: mute control for lout/rout ( table 26 ) 0: normal operation. atts3-0 bits control attenuation value. 1: mute. atts3-0 bits are ignored. (default) dattc: dac digital attenuator control mode select 0: independent (default) 1: dependent at dattc bit = ?1?, attl7-0 bits control both channel attenuation le vels, while register values of attl7-0 bits are not written to the attr7-0 bits. at dattc bit = ?0?, the attl7-0 bits control the left channel level and the attr7-0 bits control the right channel level. ats: digital attenuator transition time setting ( table 18 ) 0: 1061/fs (default) 1: 7424/fs
[ak4372] ms0684-e-02 2008/12 - 55 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h dac lch att attl7 attl6 attl5 attl4 attl3 attl2 attl1 attl0 06h dac rch att attr7 attr6 a ttr5 attr4 attr3 attr2 attr1 attr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 attl7-0: setting of the attenuation value of output signal from dacl ( table 17 ) attr7-0: setting of the attenuation value of output signal from dacr ( table 17 ) default: ?00h? (mute) addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h headphone out select 0 hpg1 hpg0 minhr minhl rinhr linhl darhr dalhl r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dalhl: dac left channel output signal is adde d to the left channel of the headphone-amp. 0: off (default) 1: on darhr: dac right channel output signal is adde d to the right channel of the headphone-amp. 0: off (default) 1: on linhl: input signal to lin pin is added to the left channel of the headphone-amp. 0: off (default) 1: on rinhr: input signal to rin pin is added to the right channel of the headphone-amp. 0: off (default) 1: on minhl: input signal to min pin is added to the left channel of the headphone-amp. 0: off (default) 1: on minhr: input signal to min pin is added to the right channel of the headphone-amp. 0: off (default) 1: on hpg1-0: dac ? hpl/r gain ( table 25 ) default: ?00?: +0.95db
[ak4372] ms0684-e-02 2008/12 - 56 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h lineout select 0 0 log minr minl rinr linl darr dall r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 dall: dac left channel output is added to the lout buffer amp. 0: off (default) 1: on darr: dac right channel output is added to the rout buffer amp. 0: off (default) 1: on linl: input signal to the lin pin is added to the lout buffer amp. 0: off (default) 1: on rinr: input signal to the rin pin is added to the rout buffer amp. 0: off (default) 1: on minl: input signal to the min pin is added to the lout buffer amp. 0: off (default) 1: on minr: input signal to the min pin is added to the rout buffer amp. 0: off (default) 1: on log: dac ? lout/rout gain 0: 0db (default) 1: +6db addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h lineout att 0 0 0 0 atts3 atts2 atts1 atts0 r/w rd rd rd rd r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 atts3-0: analog volume control for lout/rout ( table 26 ) default: lmute bit = ?1?, a tts3-0 bits = ?0000? (mute) setting of atts3-0 bits is enabled at lmute bit is ?0?.
[ak4372] ms0684-e-02 2008/12 - 57 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh headphone out select 0 0 0 0 0 0 linhr rinhl r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 rinhl: rin signal is added to the left channel of the headphone-amp 0: off (default) 1: on linhr: lin signal is added to the right channel of the headphone-amp 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh headphone att 0 hpz hmute atth4 atth3 atth2 atth1 atth0 r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 atth4-0: setting of the attenuation value of output signal from headphone ( table 25 ) default: hmute bit = ?0?, atth4-0 bits = ?00? (0db) setting of atth4-0 bits is enabled at hmute bit is ?0?. hmute: mute control for headphone-amp ( table 25 ) 0: normal operation. atth4-0 bits control attenuation value. (default) 1: mute. atth4-0 bits are ignored. hpz: headphone-amp pull-down control 0: shorted to gnd (default) 1: pulled-down by 200k (typ)
[ak4372] ms0684-e-02 2008/12 - 58 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh lineout select 0 0 0 0 0 0 linr rinl r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 rinl: rin signal is added to the left channel of the lineout 0: off (default) 1: on linr: lin signal is added to the right channel of the lineout 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h mono mixing 0 0 0 0 0 0 lm lhm r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 lhm: lin/rin signal is added to headphone-amp as (l+r)/2. 0: off (default) 1: on lm: lin/rin signal is added to lout/rout as (l+r)/2. 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h differential select 0 0 0 0 0 0 ldifh ldif r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 ldif: switch control from in+/in ? pin to lout/rout. 0: off (default) 1: on when ldif bit = ?1?, the lin1 and rin1 pins become in+ and in ? pins respectively. ldifh: switch control from the in+/in ? pin to headphone-amp. (setting of lidfh bit is enable at ldif bit = ?1?) 0: off (default) 1: on
[ak4372] ms0684-e-02 2008/12 - 59 - system design figure 50 shows the system connection diagram. the evaluation board [AKD4372] demonstrates the optimum layout, power supply arrangements and measurement results. 16 220 + 220 + 16 headphone analog supply 1.6 3.6v 10 + 10 2.2 spk-amp audio controller p 1 a nalog ground digital ground cp rp vss2 cclk csn pdn mutet vcoc mcko cdti lout rout mcki lrck i2c vcom bick hpr avdd sdata rin hpl vss1 lin min dvdd ak4372ecb top view 1000p 0.1 0.1 + notes: - vss1 and vss2 of the ak4372 should be distributed separately from the ground of external controllers. - all digital input pins (i2c, sda/cdti, scl/cclk, cad0/csn, sdata, lrck, bick, mcki, pdn) must not be left floating. - when the ak4372 is in ext mode (pmpll bit = ?0?), a resistor and capacitor for the vcoc pin are not needed. - when the ak4372 is in pll mode (pmpll bit = ?1?), a resistor and capacitor for the vcoc pin are shown in table 4 - when the ak4372 is used in master mode, lrck and bick pins are floating before the m/s bit is changed to ?1?. therefore, a 100k pull-up resistor should be connected to the lrck and bick pins of the ak4372. - when dvdd is supplied from avdd via 10 series resistor, the capacitor larger than 0.1 f should not be connected between dvdd and the ground. figure 50. typical connection diagram (in case of ac coupling to mcki)
[ak4372] ms0684-e-02 2008/12 - 60 - 110k 100k a k4372 lin1 pin avdd lin1hl bit hp-amp note: if the path is off and the signal is input to the input pi n, the input pin should be biased to a voltage equivalent to vcom voltage (= 0.475 x avdd) externally. figure 51. external bias circuit example for line input pin 1. grounding and power supply decoupling the ak4372 requires careful attention to power supply a nd grounding arrangements. avdd is usually supplied from the analog power supply in the system and dvdd is supplied from avdd via a 10 resistor. alternatively if avdd and dvdd are supplied separately, avdd should be powered-up after dvdd rises up to 1.6v or more. when the ak4372 is powered-down, dvdd should be powered-down at the same time or later than avdd. vss1 and vss2 must be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as close to the ak4372 as possible, with the small value ceram ic capacitors being the nearest. 2. voltage reference the input voltage to avdd sets the analog output range. usually a 0.1 f ceramic capacitor is connected between avdd and vss1. vcom is a signal ground of this chip (0.475 x avdd). the electrolytic capacitor around 2.2 f attached between vcom anvss1 eliminates the effects of high frequency noise, too. no load current may be drawn from the vcom pin. all signals, especially clock, should be ke pt away from avdd and vcom in order to avoid unwanted coupling into the ak4372. 3. analog outputs the analog outputs are single-ended outputs, and 0.48 x avdd vpp(typ)@ ? 3dbfs for headphone-amp, 0.61xavdd vpp(typ) @0dbfs for lout/rout centered on the vcom voltage. the input data format is 2?s compliment. the output voltage is a positive full scale for 7fffffh(@24bit) and negative full scale for 800000h(@24bit). the ideal output is vcom voltage for 000000h(@24bit). dc offsets on the analog outputs should be eliminated by ac coupling since the analog outputs have a dc offset equal to vcom plus a few mv.
[ak4372] ms0684-e-02 2008/12 - 61 - package 24pin csp (unit: mm) a b c e d 5 3 4 1 2 ed c a b 5 3 4 1 2 top view 2.50 0.05 4372 xxxx 2.50 0.05 bottom view a 0.4 0.65 0.20 0.05 0.08 s s b 0.25 0.05 0.05 ab s m material & lead finish package material: epoxy resin, halogen (bromine and chlorine) free solder ball material: snagcu
[ak4372] ms0684-e-02 2008/12 - 62 - marking a 1 4372 xxxx xxxx: date code (4 digit) revision history date (yy/mm/dd) revision reason page contents 07/10/30 00 first edition 08/12/04 01 product addition 1, 3, 4, 6 ak4372vcb was added. ambient temperature ak4372ecb: ? 30 85 c ak4372vcb: ? 40 85 c specification change 53 package material was changed. 08/12/19 02 description addition 39-42 power-up/down sequence (pll slave mode, pll master mode) were added. important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.

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